Re: [avr-gcc-list] Trouble with division

[Joerg Wunsch]

In article <address@hidden> you write:

>> About 9 months ago I wrote a small AVR program to time various operations.
>> Here are the results I got:
>> 
>> atmega103 at 4 MHz

Two notes:

The ATmega103 didn't have the hardware multiplier the advanced ATmegas
now have.  Since division IMHO includes multiplication operations,
things might be better with a newer ATmega.

Second, in particular division (but also software multiplication)
heavily depends on the operands, so no single cycle count can be
given.  Ulrich already noticed that division by a power of two goes a
lot faster than division by other numbers.  So the worst case has to
be timed if someone is interested (or just time the divisors you're
interested in).

Ulrich, the statement »1 MIPS per MHz clock« only means that hardware
math operations are done within one clock cycle.  Note that even this
statements is not fully correct, since there are few hardware math
operations that take two cycles: ADIW, SBIW, and all the hardware
multiplications.  (Among the non-artithmetical instructions, there's a
good number that takes two cycles, and notably the long CALL and RET
instructions on the ATmega128 can take up to 5 cycles.)

But, as you've seen, only the newer ATmegas can do hardware
multiplication, and none of the AVRs can do hardware division.  To be
fair, even many DSPs cannot do that.  But when it comes to software
operations, times will be way off the 1 MIPS/MHz figure, naturally.
After all, it's a microcontroller -- and even a fairly fast one in its
class, still.  (And i think, even CISC CPUs that have hardware
division have a cycle count that depends on the divisor.  Division has
always been the most expensive of the four basic arithmetic
operations, and is still today.)
-- 
J"org Wunsch                                           Unix support engineer
address@hidden        http://www.interface-systems.de/~j/