On Tue, 16 Apr 2024, Nicholas Piggin wrote: On Wed Apr 10, 2024 at 9:03 PM AEST, BALATON Zoltan wrote: On Wed, 10 Apr 2024, Nicholas Piggin wrote: On Wed Apr 10, 2024 at 9:55 AM AEST, BALATON Zoltan
Hey, travelling / at a conference / on vacation for the next couple of weeks. It's just a bit late for hard freeze IMO, since we didn't break it before the prior release or a bad security / crash bug
On Wed, 10 Apr 2024, Nicholas Piggin wrote: On Wed Apr 10, 2024 at 9:55 AM AEST, BALATON Zoltan wrote: Real 460EX SoC apparently does not expose a bridge device and having it appear on PCI bus confus
In the bad case it crashes after running this TB: -- IN: 0x00c01354: 38c00040 li r6, 0x40 0x00c01358: 38e10204 addi r7, r1, 0x204 0x00c0135c: 39010104 addi r8, r1, 0x104 0x00c01360: 39410004 addi r10
Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting MorphOS on sam460ex (this was before 8.2.0 and I thought I've verified it before that release but apparently missed it back then)
Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting MorphOS on sam460ex (this was before 8.2.0 and I thought I've verified it before that release but apparently missed it back then)
Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently buried in the depths of the qemu-devel mailing list and in the source code. Let's collect the informatio
On Thu, 29 Feb 2024, BALATON Zoltan wrote: On Wed, 21 Feb 2024, BALATON Zoltan wrote: Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently buried in the dept
On Wed, 21 Feb 2024, BALATON Zoltan wrote: Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently buried in the depths of the qemu-devel mailing list and in th
Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting MorphOS on sam460ex (this was before 8.2.0 and I thought I've verified it before that release but apparently missed it back then)
Hi Zoltan, Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting MorphOS on sam460ex (this was before 8.2.0 and I thought I've verified it before that release but apparently missed it
Hello, Commit 18a536f1f8 (accel/tcg: Always require can_do_io) broke booting MorphOS on sam460ex (this was before 8.2.0 and I thought I've verified it before that release but apparently missed it bac
Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently buried in the depths of the qemu-devel mailing list and in the source code. Let's collect the informatio
Period missing at end of sentence. s/but it has/with/ ? s/open sourced/open-sourced/ I'd add a comma after "open-sourced". Period missing at end of sentence. I'd add a comma after "Alternatively". s/
On Fri, 16 Feb 2024, Thomas Huth wrote: On 16/02/2024 01.10, BALATON Zoltan wrote: Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently burried in the depths
Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently buried in the depths of the qemu-devel mailing list and in the source code. Let's collect the informatio
On Fri, 16 Feb 2024, Thomas Huth wrote: On 16/02/2024 01.10, BALATON Zoltan wrote: Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently burried in the depths
s/burried/buried/ mailing list and in the source code. Let's collect the information in the QEMU handbook for a one stop solution. MAINTAINERS | 1 + docs/system/ppc/amigang.rst | 160 ++++++++++++++++
Documentation on how to run Linux on the amigaone, pegasos2 and sam460ex machines is currently burried in the depths of the qemu-devel mailing list and in the source code. Let's collect the informati
Ping for the above six patches. These are critical for this series and haven't had comments from maintainers for five iterations, so pardon for the annoyance. Best regards, Bernhard
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing the
I think of patches 1 - 3 more as cleanups where an attribute unused in the core is moved one level up to where it is needed. In addition, the floppy core had two attributes where only one was ever us
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing th
The modifications preserve the current design, so how is this question related to this series? I'd appreciate feedback from the maintainers indeed since this part hasn't received any comments so far.
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing th
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing the
On Tue, 2 Jan 2024, Bernhard Beschow wrote: Am 16. Dezember 2023 21:15:54 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Sat, 16 Dec 2023, Bernhard Beschow wrote: Am 16. Dezember 2023 12:53:55 U
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing the
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing the
This series implements relocation of the SuperI/O functions of the VIA south bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t branch [1] which is an extension of bringing the
On Sat, 16 Dec 2023, Bernhard Beschow wrote: Am 16. Dezember 2023 12:53:55 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Sat, 16 Dec 2023, Bernhard Beschow wrote: Documentation on how to run Li
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
On 11/7/23 15:40, BALATON Zoltan wrote: The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
You should put the error_report() line inside the if() as well, to stop the error line turning up in the logfiles/stdout. This is what we do for the various MIPS boards that ordinarily need a BIOS bl
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
On Sat, 28 Oct 2023, Bernhard Beschow wrote: Am 27. Oktober 2023 11:54:48 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: Changes in v7: - Increase default memory size to 512m to match pegasos2 and
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
On Mon, 9 Oct 2023, Mark Cave-Ayland wrote: On 09/10/2023 23:23, BALATON Zoltan wrote: On Mon, 9 Oct 2023, Mark Cave-Ayland wrote: On 08/10/2023 12:08, BALATON Zoltan wrote: The initial value for BAR
The initial value for BARs were set in reset method for emulating legacy mode at start but this does not work because PCI code resets BARs after calling device reset method. This is certainly someth
The initial value for BARs were set in reset method for emulating legacy mode at start but this does not work because PCI code resets BARs after calling device reset method. This is certainly someth
The initial value for BARs were set in reset method for emulating legacy mode at start but this does not work because PCI code resets BARs after calling device reset method. This is certainly someth
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
On Mon, 9 Oct 2023, Bernhard Beschow wrote: Am 8. Oktober 2023 11:08:58 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Sun, 8 Oct 2023, Mark Cave-Ayland wrote: On 05/10/2023 23:13, BALATON Zolta
Just curious: How can you tell the difference in real hardware whether "raw" IO ports vs. BARs mapped to IO space are used? Could you provide links to such logs? That would be very helpful to have --
On 6/10/23 00:13, BALATON Zoltan wrote: The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated
Why not play safe like: 1. add a class property such as `reset_bar_addrs[PCI_NUM_REGIONS]` 2. set all elements to zero in `pci_device_class_init()` 3. respect `reset_bar_addrs` in `pci_reset_regions(
Hi Zoltan, On 6/10/23 00:13, BALATON Zoltan wrote: The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easi
The initial value for BARs were set in reset method for emulating legacy mode at start but this does not work because PCI code resets BARs after calling device reset method. This is certainly someth
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware with patches to support AmigaOS and is very similar to pegasos2 so can be easily emulated sharing most code with pegasos2. The re
Hello, The mac99 machine (quite unintuituvely) emulates several PowerMac like machines depending on how it's used. With qemu-system-ppc -machine mac99 it emulates a G4 PowerMac3.1 which is the most t
We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some valid looking result otherwise it hangs. Add some minimal dummy implementation to
On 6/14/23 16:21, BALATON Zoltan wrote: On Mon, 5 Jun 2023, BALATON Zoltan wrote: We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some
On 6/29/23 05:36, BALATON Zoltan wrote: On Wed, 21 Jun 2023, BALATON Zoltan wrote: On Wed, 14 Jun 2023, BALATON Zoltan wrote: On Mon, 5 Jun 2023, BALATON Zoltan wrote: We don't emulate the gigabit et
On 6/29/23 10:36, BALATON Zoltan wrote: On Wed, 21 Jun 2023, BALATON Zoltan wrote: On Wed, 14 Jun 2023, BALATON Zoltan wrote: On Mon, 5 Jun 2023, BALATON Zoltan wrote: We don't emulate the gigabit et
On Wed, 21 Jun 2023, BALATON Zoltan wrote: On Wed, 14 Jun 2023, BALATON Zoltan wrote: On Mon, 5 Jun 2023, BALATON Zoltan wrote: We don't emulate the gigabit ethernet part of the chip but the MorphOS
On Wed, 14 Jun 2023, BALATON Zoltan wrote: On Mon, 5 Jun 2023, BALATON Zoltan wrote: We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get so
On Wed, 14 Jun 2023, Cédric Le Goater wrote: On 6/8/23 11:34, BALATON Zoltan wrote: On Thu, 8 Jun 2023, Cédric Le Goater wrote: On 6/7/23 00:02, BALATON Zoltan wrote: Count exceptions which can be
We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some valid looking result otherwise it hangs. Add some minimal dummy implementation to
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel This series improves embedded PPC TLB emulation a bit and contains some misc clean up I've found along the way. Before this patch ppce
This series is split off from a more general PCI IDE refactoring aiming for a common implementation of the PCI IDE controller specification for all TYPE_PCI_IDE models [1]. The first three patches re
Hello, This series improves embedded PPC TLB emulation a bit and contains some misc clean up I've found along the way. Before this patch ppcemb_tlb_check() shows up in a memory access intensive profi
This series is split off from a more general PCI IDE refactoring aiming for a common implementation of the PCI IDE controller specification for all TYPE_PCI_IDE models [1]. The first three patches re
This series is split off from a more general PCI IDE refactoring aiming for a common implementation of the PCI IDE controller specification for all TYPE_PCI_IDE models [1]. The first three patches re
On Mon, 24 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 19:21:12 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Sat, 22 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 17:23:56 UTC sc
Indeed. I've updated my copy of the datasheet. I'll try to find the Debian ISO to test with pegasos2.rom. I see it now. I'll use hardcoded IRQs 14 and 15 then. Best regards, Bernhard
On Sun, 23 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 21:10:14 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Sat, 22 Apr 2023, Bernhard Beschow wrote: Allows to unexport pci_ide_{cmd,d
Indeed. It's now the other way around. BARs 0-3 are the PCI-native BARs and BAR4 is the BMDMA BAR which are mapped by via and cmd646 already since they support these modes. SIL3112 supports these mod
On Sat, 22 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 17:23:56 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Sat, 22 Apr 2023, Bernhard Beschow wrote: The VIA south bridge allows the l
In the datasheet titled "VT8231 South Bridge", preliminary revision 0.8, Oct. 29, 1999, page 60, the "IDE Interrupt Routing" register is located at offset 0x4a and offers the same four interrupts in
On Sat, 22 Apr 2023, Bernhard Beschow wrote: The VIA south bridge allows the legacy IDE interrupts to be routed to four different ISA interrupts. This can be configured through the 0x4a register in t
This series is yet another attempt to clean up the PCI IDE models. It is mainly inspired the Mark's invaluable input from previous discussions. In particular, this series attempts to follow the "PCI
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts
Hi Zoltan, According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts
Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 data
On Tue, 7 Mar 2023, Alex Bennée wrote: BALATON Zoltan <balaton@eik.bme.hu> writes: On Tue, 7 Mar 2023, Mark Cave-Ayland wrote: On 07/03/2023 00:20, BALATON Zoltan wrote: On Mon, 6 Mar 2023, Mark Cav
Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 data
<snip> This sort of passive aggressive framing isn't helpful or conducive to collaboration. We should be striving to merge code based on the merits of the patches not on how close we are to a given r
Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 data
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts
Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 data
On Tue, 7 Mar 2023, Mark Cave-Ayland wrote: On 06/03/2023 22:00, BALATON Zoltan wrote: On Mon, 6 Mar 2023, Mark Cave-Ayland wrote: On 06/03/2023 12:33, BALATON Zoltan wrote: According to the PegasosI