On Sat, 25 Feb 2023, Philippe Mathieu-Daudé wrote: On 21/2/23 19:44, BALATON Zoltan wrote: According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv6
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts
On Sat, 25 Feb 2023, Philippe Mathieu-Daudé wrote: On 21/2/23 19:44, BALATON Zoltan wrote: According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv6
On 21/2/23 19:44, BALATON Zoltan wrote: According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 so
On 2/21/23 15:44, BALATON Zoltan wrote: According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 so
The datasheet says so. It says that 0x55-0x57 are controlling what ISA interrupts the PIRQA-D pins should raise while internal functions are documented to have 0x3c register to select what ISA IRQ t
I hope that I could help you get a better understanding. The linked .pdf is good and comprehensive reading material. I'm not sure the via-ide confirms to that doc but it's also not any more a problem
On Tue, Feb 21, 2023 at 7:44 PM BALATON Zoltan <balaton@eik.bme.hu> wrote: This series fixes PCI interrupts on the ppc/pegasos2 machine and adds partial implementation of the via-ac97 sound part enou
According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts
On Thu, 19 Jan 2023, Dan Whitehouse wrote: I’m running Debian from ports (64-bit) on my G5 as the host. Thanks for your advice - attempting to install a 64-bit Debian guest was my next target, alth
On Thu, 1 Sep 2022, Bernhard Beschow wrote: On Wed, Aug 31, 2022 at 6:02 PM BALATON Zoltan <balaton@eik.bme.hu> wrote: On Wed, 31 Aug 2022, BB wrote: Am 31. August 2022 17:03:35 MESZ schrieb BALATON
On Wed, 20 Oct 2021, Cédric Le Goater wrote: On 10/20/21 13:42, BALATON Zoltan wrote: On Wed, 20 Oct 2021, Philippe Mathieu-Daudé wrote: On 10/5/21 14:29, Thomas Huth wrote: I think there are many
Hi Zoltan, i have same issue with kvm with only qemu-system-ppc -M pegasos2 -bios pegasos2.rom --enable-kvm and with this command line that work great on my PC (without kvm of course) qemu-system-ppc
Hello, OK. Can you also show the full command so we know what options you used? via_superio_cfg: unimplemented register 0xf2 via_superio_cfg: unimplemented register 0xf4 via_superio_cfg: unimplemente
On 09/07/2021 23:28, BALATON Zoltan wrote: On Fri, 9 Jul 2021, Alexey Kardashevskiy wrote: On 09/07/2021 08:34, BALATON Zoltan wrote: MorphOS still boots but this breaks Linux which changes a few thi
What are those things? What does the change break precisely? Does the kernel stop booting? Can you please send output with the trace_vof_setprop tracepoint enabled? It's fixing up some props that on
The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes that are not open source therefore the ROM binary cannot be included in QEMU. Guests runnin
Applied to ppc-for-6.1, thanks. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ http://www.ozlabs.org/~dgibson Atta
With this series on top of VOF v22 I can now boot Linux and MorphOS on pegasos2 without a firmware blob so I hope this is enough to get this board in 6.1 and also have it enabled so people can start
The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes that are not open source therefore the ROM binary cannot be included in QEMU. Guests runnin
With this series on top of VOF v22 I can now boot Linux and MorphOS on pegasos2 without a firmware blob so I hope this is enough to get this board in 6.1 and also have it enabled so people can start
On Wed, 16 Jun 2021, Philippe Mathieu-Daudé wrote: On 6/16/21 10:01 PM, BALATON Zoltan wrote: On Wed, 16 Jun 2021, Philippe Mathieu-Daudé wrote: On 6/16/21 9:16 PM, Corey Minyard wrote: On Wed, Jun
On 16/06/2021 20:26, BALATON Zoltan wrote: On Wed, 16 Jun 2021, Alexey Kardashevskiy wrote: On 6/16/21 07:09, BALATON Zoltan wrote: On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote: The PAPR platform
I understand your concern, but these sorts of interfaces are really just asking for trouble, as you experienced and as seen by the other patch that fixed an error using the same interface. It's bette
On Wed, 16 Jun 2021, Philippe Mathieu-Daudé wrote: On 6/16/21 10:01 PM, BALATON Zoltan wrote: On Wed, 16 Jun 2021, Philippe Mathieu-Daudé wrote: On 6/16/21 9:16 PM, Corey Minyard wrote: On Wed, Jun
On Wed, 16 Jun 2021, Alexey Kardashevskiy wrote: On 6/16/21 07:09, BALATON Zoltan wrote: On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote: The PAPR platform describes an OS environment that's presente
On 6/16/21 07:09, BALATON Zoltan wrote: On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote: The PAPR platform describes an OS environment that's presented by a combination of a hypervisor and firmware.
Since the beginning, the runtime component of the firmware (RTAS) has been implemented as a 20 byte shim which simply forwards it to a hypercall implemented in qemu. The boot time firmware component
On 6/7/21 01:46, BALATON Zoltan wrote: The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes that are not open source therefore the ROM binary ca
Hello, Posting these for early review now. I plan to rebase on the next VOF patch that hopefully fixes those points that I had to circumvent in patch 1 for now. I've reported these before but now all
The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes that are not open source therefore the ROM binary cannot be included in QEMU. Guests runnin
Hello, Posting these for early review now. I plan to rebase on the next VOF patch that hopefully fixes those points that I had to circumvent in patch 1 for now. I've reported these before but now all
I'm confused, I thought you just said that it looked for both isa@c and isa@C, which seems to contradict guests always using lower case. -- David Gibson | I'll have my music baroque, and my code davi
On Tue, 1 Jun 2021, Alexey Kardashevskiy wrote: On 31/05/2021 23:07, BALATON Zoltan wrote: On Sun, 30 May 2021, BALATON Zoltan wrote: On Thu, 20 May 2021, Alexey Kardashevskiy wrote: diff --git a/hw/
On Mon, 24 May 2021, David Gibson wrote: On Mon, May 24, 2021 at 02:26:42PM +1000, Alexey Kardashevskiy wrote: On 5/23/21 21:24, BALATON Zoltan wrote: On Sun, 23 May 2021, Alexey Kardashevskiy wrote:
IIUC, it's basicaly so that the 'sc 1' instructions can be routed through to VOF. 'sc 1' is an illegal instruction on ppc32, AFAIK, so we need some sort of hack here. vhyp wasn't really designed for
On 5/23/21 21:24, BALATON Zoltan wrote: On Sun, 23 May 2021, Alexey Kardashevskiy wrote: On 23/05/2021 01:02, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, Ale
On Sun, 23 May 2021, Alexey Kardashevskiy wrote: On 22/05/2021 23:08, BALATON Zoltan wrote: On Sat, 22 May 2021, Alexey Kardashevskiy wrote: On 22/05/2021 05:57, BALATON Zoltan wrote: On Fri, 21 May
On Sun, 23 May 2021, Alexey Kardashevskiy wrote: On 23/05/2021 01:02, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, Alexey Kardashevskiy wrote: VOF itself does
On 22/05/2021 23:08, BALATON Zoltan wrote: On Sat, 22 May 2021, Alexey Kardashevskiy wrote: On 22/05/2021 05:57, BALATON Zoltan wrote: On Fri, 21 May 2021, BALATON Zoltan wrote: On Fri, 21 May 2021,
On 23/05/2021 01:02, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, Alexey Kardashevskiy wrote: VOF itself does not prints anything in this patch. However it se
However it seems to be needed for linux as the first thing it does seems to be getting /chosen/stdout and calls exit if it returns nothing. So I'll need this at least for linux. (I think MorphOS may
On Sat, 22 May 2021, Alexey Kardashevskiy wrote: On 22/05/2021 05:57, BALATON Zoltan wrote: On Fri, 21 May 2021, BALATON Zoltan wrote: On Fri, 21 May 2021, Alexey Kardashevskiy wrote: On 21/05/2021 0
On 22/05/2021 05:57, BALATON Zoltan wrote: On Fri, 21 May 2021, BALATON Zoltan wrote: On Fri, 21 May 2021, Alexey Kardashevskiy wrote: On 21/05/2021 07:59, BALATON Zoltan wrote: On Thu, 20 May 2021,
On 21/05/2021 19:05, BALATON Zoltan wrote: On Fri, 21 May 2021, Alexey Kardashevskiy wrote: On 21/05/2021 07:59, BALATON Zoltan wrote: On Thu, 20 May 2021, Alexey Kardashevskiy wrote: The PAPR platfo
On Fri, 21 May 2021, BALATON Zoltan wrote: On Fri, 21 May 2021, Alexey Kardashevskiy wrote: On 21/05/2021 07:59, BALATON Zoltan wrote: On Thu, 20 May 2021, Alexey Kardashevskiy wrote: The PAPR platfo
On Fri, 21 May 2021, Alexey Kardashevskiy wrote: On 21/05/2021 07:59, BALATON Zoltan wrote: On Thu, 20 May 2021, Alexey Kardashevskiy wrote: The PAPR platform describes an OS environment that's prese
On Wed, 10 Mar 2021, BALATON Zoltan wrote: In VIA super south bridge the io ranges of superio components (parallel and serial ports and FDC) can be controlled by superio config registers to set their
On Tue, 16 Mar 2021, Mark Cave-Ayland wrote: On 16/03/2021 13:06, BALATON Zoltan wrote: The PATCH 1 doesn't seem to be needed to have a working Pegasos 2 machine, does it? It is needed (as well as a
I've queued these to ppc-for-6.0. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ http://www.ozlabs.org/~dgibson At
On Fri, 12 Feb 2021, Peter Maydell wrote: For a long time now the UI layer has guaranteed that the console surface is always 32 bits per pixel RGB, but some older display device models still have the
This fixes a long standing issue with MorphOS booting on sam460ex which turns out to be because of suspicious values written to PCI config address that apparently works on real machine but caused wro
This fixes a long standing issue with MorphOS booting on sam460ex which turns out to be because of suspicious values written to PCI config address that apparently works on real machine but caused wro
On Mon, 4 Jan 2021, David Gibson wrote: On Sun, Jan 03, 2021 at 02:09:33AM +0100, BALATON Zoltan via wrote: So this is v3 of a series that started to fix a potential problem with irq mapping in pci44
Applied to ppc-for-6.0. So.. you're pretty much the only person who's shown any interest in the embedded ppc stuff in qemu for a pretty long time. Any chance I could convince you to be ppc4xx submain
This fixes a long standing issue with MorphOS booting on sam460ex which turns out to be because of suspicious values written to PCI config address that apparently works on real machine but caused wro
So this is v3 of a series that started to fix a potential problem with irq mapping in pci440_pcix (used by sam460ex) that got some other fixes along the way as by-products. But it turns out the irq i
Thanks for doing this clean up. this fixes a couple of long-standing trivial Coverity issues -- the current ppcuic_init() function allocates an array of qemu_irqs which the callers then leak. (The le
MorphOS writes to PCI_CLASS_PROG during IDE initialisation to place the controller in native mode, but thinks the initialisation has failed because the native mode bits aren't set when reading the re
This is an RFC series to start exploring the possibility of enabling hardfloat for PPC target that haven't progressed in the last two years. Hopefully we can work out something now. Previously I've e
I think the ideal would be to test against a reference using risu to see whether this changes behaviour (FP results should be bit-for-bit identical; usually application level testing is often not suf
Hello, This is an RFC series to start exploring the possibility of enabling hardfloat for PPC target that haven't progressed in the last two years. Hopefully we can work out something now. Previously
Hello, On Tue, 30 Jul 2019, luigi burdo wrote: the issue on the color on Linux PPC with ati/radeon/amd was present from 3.x kernel. the only way for have right colors on real hardware is the use of t
Hello, In order for the rom based or disk based ATI ‘NDRV’ to load for the Rage128, the name string needs to match in name space. I.E. ATY,Rage128Pd as the name property rather than just ATY. Yes
Some observation that I’m not sure is useful: OS X never maps the vram and is unable to load the graphics server in any mode other than 8 bits color. The last thing we see in a successful graphics
В сообщении от Tuesday 09 July 2019 19:27:30 BALATON Zoltan написал(а): I think this is one of those 32-bit only crashes, because I booted same iso with 64-bit qemu without crash
В сообщении от Tuesday 09 July 2019 13:13:05 BALATON Zoltan написал(а): Unfortunately, it crashes otherwise for me : / (on 32-bit qemu). It even crash if I add only ES1370 device,
On Wed, 3 Jul 2019, Philippe Mathieu-Daudé wrote: On 7/2/19 11:52 PM, BALATON Zoltan wrote: On Tue, 2 Jul 2019, Peter Maydell wrote: Currently the bitbang_i2c_init() function allocates a bitbang_i2c
On Tue, 2 Jul 2019, Peter Maydell wrote: Currently the bitbang_i2c_init() function allocates a bitbang_i2c_interface struct which it returns. This is unfortunate because it means that if the function
On 1/27/19 7:19 AM, Mark Cave-Ayland wrote: Could this make the loop slower? I certainly haven't noticed any obvious performance difference during testing (OS X uses merge quite a bit for display re
Right. As I mentioned in an earlier email, this is hopefully laying the groundwork for future evolution of the TCG vector operations and making use of the existing functions first. Certainly I'd be i
I should clarify here. When I say "floating point" above, I'm not meaning things using the regular FPU instead of the vector unit. I'm saying *anything* involving floating point calculations whether
On Mon, 10 Dec 2018, David Gibson wrote: On Mon, Dec 10, 2018 at 01:33:53AM +0100, BALATON Zoltan wrote: On Fri, 7 Dec 2018, Mark Cave-Ayland wrote: This patchset is an attempt at trying to improve t
What was your host machine. IIUC this change will only improve performance if the host tcg backend is able to implement TCG vector ops in terms of vector ops on the host. In addition, this series onl
This is very welcome, thanks for doing this. In order to use TCG vector operations, the registers must be accessible from cpu_env whilst currently they are accessed via arrays of static TCG globals.
On Tue, 17 Jul 2018, Mark Cave-Ayland wrote: On 17/07/18 20:35, BALATON Zoltan wrote: On Tue, 17 Jul 2018, Mark Cave-Ayland wrote: MorphOS on mac99 this seems to be significant. This is with default
This seems to depend on the workload. From the cases I'm interested in AROS and AmigaOS on qemu-system-ppc -M sam460ex does not seem to be effected much (object_class_dynamic_cast_assert is not in to
This seems to depend on the workload. From the cases I'm interested in AROS and AmigaOS on qemu-system-ppc -M sam460ex does not seem to be effected much (object_class_dynamic_cast_assert is not in to
The PPC440 User Manual says that if bit 31 is set, the contents of CR[CR0] are undefined for indexed store instructions but this form is not invalid. Other PPC variants confirming to recent ISA where
Applied to ppc-for-3.0, thanks. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ http://www.ozlabs.org/~dgibson Atta
Right. I haven't forgotten it, I just hadn't yet found time to research the change a bit more thorougly. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | min
On Fri, 29 Jun 2018, David Gibson wrote: On Fri, Jun 29, 2018 at 02:48:40PM +1000, David Gibson wrote: On Fri, Jun 29, 2018 at 12:38:33AM +0200, BALATON Zoltan wrote: PPC440 SoCs such as the AMCC 460
The PPC440 User Manual says that if bit 31 is set, the contents of CR[CR0] are undefined for indexed store instructions but this form is not invalid. Other PPC variants confirming to recent ISA where
On Wed, 6 Jun 2018, David Gibson wrote: On Mon, Jun 04, 2018 at 01:50:40AM +0200, BALATON Zoltan wrote: I2C emulation currently is just enough for U-Boot to access SPD EEPROMs but features that guest
I guess the --with-*abi options are defaults now anyway so should not be explicitely needed (but it does not hurt either). I have the sam460 uboot logo from uboot but i dont know how to attach the se
Hi, i been build last git test target of qemu with ./configure --target-list=ppc-softmmu,ppc64-softmmu --audio-drv-list=sdl,pa --with-sdlabi=2.0 --with-gtk-abi=3.0 I have the sam460 uboot logo from u
I could not find this command either in the old u-boot but also not in the newer 2015.a version so I'm not sure where is it. But u-boot has bdinfo command which prints some frequencies. message in mo
Remaining patches for Sam460ex emulation. The original cover letter with more details is here: http://lists.nongnu.org/archive/html/qemu-ppc/2017-08/msg00112.html We'll need to also add binaries for
Hi Zoltan, right chooice because internal sata on sam460 had issue and wont boot os4,morphos... only the cdrom was booting if i remember good from internal sata 0. personally when i had a Sam460ex i
It may help if you can do that. You need to compile QEMU from git with this patch series applied and copy the u-boot-sam460-20100605-fixed.bin linked from the cover message as u-boot-sam460-20100605.